1. Field of the Invention
The present invention relates a method and architecture of controlling an active pixel element, and more particularly, to a method and architecture of controlling an active pixel element sequence.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 refers to a diagram of an active pixel element 10 of an image sensor array 1 according to the prior art. The active pixel element 10 includes a sensor 12, a transfer transistor 14, a reset transistor 16, and a source follower 18. As the operation between the transistors 14-18 and the sensor is well known to those having average skilled in this art, therefore further detailed explanation will not be reiterated for the sake of brevity.
A read circuit is utilized for reading the signal of each column of the active pixel element 10 of the image sensor array 1. The reading circuit 22 includes a reset signal switch (SHR) 24 and a light signal switch (SHS) 26 for respectively controlling storage of the reset signal and the light signal. Furthermore, a power source 28 is for providing power to the active pixel element 10 of a same row.
Please refer to FIG. 2. FIG. 2 illustrates a time sequence diagram of controlling the active pixel element 10 of the image sensor array 1 of FIG. 1 and two switches 24, 26 of a read circuit 22. FIG. 2 illustrates an example of controlling the sequence of the active pixel element 10 at a 0th row in an exposure state, when the sensor 12 of the active pixel element 10 at the 0th row is being reset, the transfer transistor 14 of the 0th row will be turned on while the reset transistor 16 is still turned on until the transfer transistor 14 is turned off to execute exposure after the 0th row.
The active pixel element 10 is unable to record gate voltage of the source follower 18 when exposure is executed, therefore an initial voltage must be created for the light signal, and a reset signal must be read before reading the light signal. So, in a CDS dumping data state, when the reset signal of the active pixel element 10 at the 0th row is being read, the SHR 24 is turned on, and the reset transistor 16 of the 0th row is also turned on to read the reset signal. Next, the SHR 24 and the reset transistor 16 are turned off, and the SHS 26 and the transfer transistor 14 of the 0th row are turned on to read the light signal.
As illustrated in FIG. 2, the size of reset reference voltage of the active pixel element 10 during the execution of the reset operation and the size of reset reference voltage during the reading of the reset signal are similar, thus there will not be a problem caused by a difference of reset reference voltages under the two different statuses. However, a problem does arise, as there is a reset reference voltage difference between each column and between each row in the image sensor array.
Please refer to FIG. 3. FIG. 3 illustrates a diagram of a voltage drop generated between each column on a same row of the image sensor array 1 of FIG. 1. When the reset operation is executed, all the source followers 18 on the 0th row will still be turned on, as current generated by the source follower 18 on the 0th row and impendence of the power cable of the power source 28 form a voltage drop, each active pixel element 10 of the 0th row will have a different reset reference voltage. Similarly, as power is respectively provided to each row, therefore impendence of the power cable of each row is different, furthermore, there is a difference in the current drop generated by each source follower 18 on each different row, hence there is also a problem of the reset reference voltage being different among each row in the image sensor array 1, which can cause a serious difference in the initial exposure value (EV).
Please refer to FIG. 4. FIG. 4 illustrates a diagram of an active pixel element 30 of an image sensor array 3 according to another prior art. The difference with the active pixel element 30 and the active pixel element 10 lies in a row selector 20. Furthermore, a power source 32 of FIG. 3 is utilized for providing power to all active pixel elements 30 of the image sensor array 3.
Please refer to FIG. 5. FIG. 5 illustrates a time sequence diagram of controlling the active pixel element 30 of the image sensor array 3 of FIG. 3 and two switches 24, 26 of a read circuit 22. FIG. 5 illustrates an example of controlling the sequence of the active pixel element 30 at the 0th column, when the sensor 12 of the active pixel element 30 at the 0th column is being reset, the transfer transistor 14 and the reset transistor 16 of the 0th column will be turned on and the row selector 20 is turned off, as this time maybe the time of reading the light signal at an Xth column, until the transfer transistor 14 and the reset transistor 16 are respectively turned off to execute exposure after the 0th column.
At the same time the sensor 12 of the 0th column is being reset, the active pixel element 30 of the Xth column is at a signal reading status, thus the row selector 20 of the Xth column is still turned on, and all the source followers 18 of the Xth column are still turned on, therefore the reset reference voltage will be lowered to V1, if this value subtracts a threshold voltage of the reset transistor 16, then the result will be a gate voltage of the source follower 18, which is also the initial voltage of the light signal.
When the reset signal of the active pixel element 30 of the 0th column is being read, the reset signal switch 24 is turned on, the row selector 20 and the reset transistor 16 are also turned on to read the reset signal. However, at this time the reset reference voltage is V2 and not V1, this is because all the row selectors 20 of the 0th column are turned on, and none of the row selectors 20 of the Xth column are turned on, there is current flowing into the source follower 18 of the 0th column, and there is a slight difference between the actual characteristics of transistor and the power cable, which causes different voltage drops in the reset reference voltage. Therefore, the initial voltage of the light signal that is read is the threshold voltage of the reset transistor 16 subtracted from the voltage V2.
Therefore, when the reset signal is read, the drain voltage of the reset transistor 16 is V2, which is different from the drain voltage V1 of the reset transistor 16 when exposure is executed, in another words, the reset reference voltage of each active pixel element 30 of the image sensor array 3 at two different status is different. As for an active pixel element 30, the problem of the reset reference voltage difference is present when the reset operation is executed and when the reset signal is read. And as for the image sensor array 3, the problem of reset reference voltage difference between each column and between each row is also present.